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As IC applications have multiplied over the past decade, pushing CMOS electronics beyond the PC and into everything from greeting cards to the human body, so have problems associated with nano-scale high performance CMOS. The quest for improved performance, previously masked by the progression of Moore's law, now calls for renewed creativity and the development of fundamentally new approaches to circuit and architecture design. In our group, we consider how the progression of CMOS digital electronics and devices optimized for digital performance has affected mixed signal circuit design. We conduct research investigating new approaches to cost effective design that leverage today's technology but achieve improved performance per unit power. We look at how problems resulting from device scaling such as process variation, noise, and reduced analog performance can be addressed with skillful analog and mixed signal design.

Table of Contents

  1. Integrated Wireless Neurochemical Monitoring System [ACTIVE]
  2. Narrowband Interference Rejection in Wideband systems [ACTIVE]
  3. Ultra Low Power Impulse Radio Based Transceiver for Sensor Networks [ACTIVE]
  4. Real Time Signal Processing Utilizing Dispersive Devices [ACTIVE]
  5. Circuits Design with Reduced Process Variation [ACTIVE]
  6. Performance Evaluation with On-chip Optics for Future Bus Based CMPs [FINISHED]
  7. Short Link Optical Interconnects for Multi-core Processor Design [FINISHED]
  8. Low Power Receiver for Wireless Sensor Networks [FINISHED]
  9. Electrical Isolation and On-Chip Interconnects [FINISHED]
  10. Monolithically Integrated SiGe HBT Photodetector and Optical Receiver [FINISHED]
  11. Integrated Polymer Waveguide with SiGe Phototransistors and SiGe MOW [FINISHED]
  12. Electronic-Photonic Integrated Circuits (EPIC) [FINISHED]
  13. High Precision Frequency Control [FINISHED]
  14. Silicon on Sapphire Receiver Array [FINISHED]
  15. The 0.25 µm SOS CMOS 10 Gbps Receiver Project [FINISHED]

Integrated Wireless Neurochemical Monitoring System {Carlos Dorta-Quinones and Rajeev Dokania} [ACTIVE]

Existing electrochemical biosensors used for in-vivo measurements of neurotransmitter release in the brain of rats incorporate external data acquisition systems that impose a significant amount of stress and severely restrict movement of the rats under test. We propose a low-cost, low-power wireless biomedical implant that overcomes the typical limitations of tethered recording setups in order to enable stress-free, real-time monitoring of dopaminergic activity in freely moving rats. Performing real-time background subtraction techniques on-chip before digitization of the neurochemical signal improves significantly the dynamic range of the data acquisition system and also enables the integration of low-cost medium-resolution data converters consuming minimal power and real estate with a performance equivalent to their high-resolution discrete-component counterparts.

Narrowband Interference Rejection in Wideband systems {Wacek Godycki, Rajeev Dokania and Xiao Wang} [ACTIVE]

Ultra wide band impulse radio (UWB-IR) exploits extreme amplitude modulation (AM) by sending only 2ns wide pulses. The signaling in UWB-IR typically corresponds to a channel bandwidth of approximately 500MHz or greater. The receiver in UWB-IR implementations usually utilizes non-coherent energy detection, which also reduces complexity and more importantly, power consumption. However, wide channel bandwidth makes the radio susceptible to jamming, as an in-band narrowband interferer can easily corrupt the channel. Although, a notch filter can be used, this approach cuts down the UWB signal strength around the two bands. As a result, the channels around the two bands where the narrowband interferers are expected must be abandoned, cutting down on available spectrum. An interesting solution to the problem is using the Teager-Kaiser operator, which down-converts the in-band narrowband signal to close to DC, where subsequent high-pass filter ensures complete removal of the interferer. This effectively achieves a very high quality notch filter without any pre-knowledge of the center frequency of the interferer. The T-K operator exploits the temporal correlation of the signal in narrow-band signaling (slow changing information) to discriminate against fast changing wide-band impulse signaling and can be very effective in removal of narrow-band interferers.

Ultra Low Power Impulse Radio Based Transceiver for Sensor Networks {Xiao Wang and Rajeev Dokania} [ACTIVE]

Ultra-wideband (UWB) radio has been proposed as a method for short range wireless communications. The low duty cycle nature of UWB can in principle, lead to large power savings by allowing power hungry RF subsystems to remain inactive for long periods of the transmission. To date, this power savings potential has not been realizable because the nature of UWB communications necessitates time synchronization between transmitter and receiver. To achieve this time synchronization, proposed UWB architectures have invariably used fast ADCs, high performance PLLs, and DSP back-ends. These components increase the overall power requirement. Achieving synchronization without the use of these components would tremendously lower the power requirement of any wireless transceiver. We propose using the pulse coupled oscillator (PCO) phenomenon as such an alternative synchronization scheme. Sensor network nodes implementing the PCO state function are guaranteed to converge towards phase lock, with no need for a PLL or any high speed components. So far we have demonstrated synchronization both on breadboard and in simulation in the IBMCMOS7RF process. The next step is to use this synchronization to demonstrate low power active communications in the 10-20 µW range.

Real Time Signal Processing Utilizing Dispersive Devices{Bo Xiang} [ACTIVE]

The chirped signal is capable of real time signal processing. In the chirped signal, the different frequency components are assigned with different time locations. The dispersive delay line (DDL) served as a lens in time, the different frequency components will spread out in time, we have already demonstrated the stretching and compressing the pulse using this idea.

Circuits Design with Reduced Process Variation {Xuan Zhang, Mustansir Mukadam, Ishita Mukhopadhyay} [ACTIVE]

With technology scaling, circuit engineers face tremendous challenges in designing robust circuits. Among all the circuit-design challenges posed by deep sub-micron technologies (tolerating process variations, managing power budgets, meeting performance goals and overcoming short-channel effects), tolerance to process variations is emerging as the most important one. The histogram showed in Figure 1 illustrates how transistor output current may vary across multiple wafer runs, which is a vivid example of process variation. This is especially true for analog circuits; on-die and wafer-scale variations in transistors can result in a number of problems including unpredictable bias conditions, band width, skew, VCO frequency and tuning range. These challenges call for a design-stage statistical analysis and a systematic design methodology to achieve maximum yield.

Figure 1. Transistor output current across multiple wafer runs and for three specific runs.

As a step in this direction, we propose a bottom-up approach towards process-invariant circuit design. Starting at the sub-circuit level, we have built various basic circuit blocks that have significantly-reduced process, supply voltage, and temperature sensitivity:

  • Current Source

We have developed a promising design methodology based on device-level correlation to reduce the effect of intrinsic process variations without the need for post-fabrication efforts. Based upon this methodology, We have designed and optimized an example current source circuit, and measured it to have more than a factor of 2 improvement in normalized standard deviation over equivalent uncompensated current sources. The scaling behavior of the process-invariant current source in future technology nodes is found to remain unchanged despite the worsening process variability of single transistors at smaller technology nodes.

  • Frequency Reference

Figure 2. Simulation results show less than 2% normalized standard deviation over different oscillation periods (T) can be achieved in our successive approximation based VCO system over a frequency range from 5GHz to 10GHz.

Responsible for generating the "heart-beat" of the system, the frequency reference can "make-or-break" the whole system, and its variability will directly affect the overall yield. We have investigated the application of both open-loop and closed-loop feedback in process compensation with low variation ring oscillator. The carefully-designed compensation schemes are able to reduce the variation in the center frequency by more than 80%, meaning a factor of 5 improvement. They show great potential to confine the standard deviation of center frequency within 1%, making possible a fully-integrated self-calibrated self-adjusted stable frequency generator for application in microcontrollers and wireless sensor networks.

  • Low Noise Amplifier

Figure 3. Histogram of Variation of Gain of LNA with and without compensation method

Low Noise Amplifiers (LNA)- the first active block in a receiver chain - have to be extremely robust to variations in process, temperature, and supply voltage, to maintain the receiver's noise and intermodulation specifications. We focus on designing process compensating circuit blocks to minimize the variation in the gain of an LNA with the help of statistical feedback mechanisms. The circuits we have designed in the TSMC 65nm process are successfully able to reduce the variation in gain of conventional LNA systems by over 70%.

  • Data Converter
Digital-to-analog converters (DAC) for calibration purposes need to be highly accurate. But due to process variations, the accuracy of these DACs is affected. The differential nonlinearity (DNL) and the integral nonlinearity (INL) are two of the parameters to measure the accuracy of the DACs. There are 3 types of current steering DACs-thermometer coded, binary coded and segmented, which is a mix of the thermometer and binary. The thermometer coded DACs are most accurate at the expense of area. It has been shown that adding redundancy helps in reducing the DNL and the INL and thus improving the accuracy. Another method to reduce the INL in thermometer coded DAC is reordering the way the current sources are switched on and added to the output current.

Figure 4. DNL and INL improvement

Our next step is to come up with more building blocks with low variation, and hopefully to set up a whole tool kit for analog circuit design.

Performance Evaluation with On-chip Optics for Future Bus Based CMPs {N. Kirman, M. Kirman, Rajeev Dokania, Matthew A. Watkins} [FINISHED]

Technology scaling will soon allow tens or even hundreds of cores on a die. With so much of computation power on a single die comes the requirement for being able to feed them with data adequately. This poses problems for both off-chip and on-chip bandwidths. For the off-chip bandwidth, which is severely constrained by off-chip electrical data speed and pin-bandwidth, researchers are already looking at optics. In this collaborative project we go one step further and make a case for on-chip optical interconnect for future CMPs to move the data around different caches in a coherent manner. Within reasonable area and power constraints we conceptualize a hybrid electro-optical bus for on-chip communication. We then assess performance of the proposed architecture against the baseline electrical interconnects for future generation of technology.

Short Link Optical Interconnects for Multi-core Processor Design {Mustansir Mukadam} [FINISHED]

The increasing need for high speed communication among cores in a multiprocessor system and the limitations of supporting such data rates with a purely electrical medium, has seen the shift to an opto-electronic communication backplane. The aim is to integrate all elements necessary for this form of communication - modulators, waveguides, photo detectors, receivers - for a low power (1fJ/bit), high speed ( > 10Gbps) application. The OEVLSI lab is part of an interdisciplinary team working on developing a multi-core processor with on-chip optical interconnects to support such design goals.

Low Power Receiver for Wireless Sensor Networks {Zhongtao Fu} [FINISHED]

Wireless sensor networks are networks composed with micro-sensors and wireless communication transceivers. These small devices are extremely low power and cheap with the potential to be disseminated in large quantities. Inspired engineers can easily find applications of data gathering for the medical health care, traffic control and environmental monitoring. These nodes, powered by environment scavenged energy or battery, require power consumption to be around 100µW or less. Since the Phase Locked Loop (PLL) is an essential building block of these transceivers, the low power VCO and PLL designs have drawn the most attention for this application. New methodologies, matrix and circuits are under investigation for this goal.

Electrical Isolation and On-Chip Interconnects {Anand Pappu} [FINISHED]

At distances much shorter than one meter, delay and power consumption inherent to the electrical-to-optical and optical-to-electrical conversion circuitry degrade the performance of optical point-to-point signaling. However, by utilizing other advantages of optical signaling such as electrical isolation, we show in theory that even links shorter than 1 cm can demonstrate a clear advantage over electrical links [1,2]. In addition, we designed and fabricated proof-of-concept circuits to validate our theory and demonstrate the advantages of electrical isolation [3].

  • [1] Anand Pappu and Alyssa Apsel, “Electrical Isolation and Fan-out in Intra-chip Optical Interconnects? Proceedings of the International Conference on Circuits and Systems 2004
  • [2] Anand Pappu and Alyssa Apsel, “Analysis of Intra-Chip Electrical and Optical Fanout? Submitted to Applied Optics, December 2004
  • [3] Anand Pappu and Alyssa Apsel, “A Low-Power, Low-Delay TIA for On-Chip Applications? Conference on Lasers and Electro-Optics, May 2005

However what is stopping the development of optical interconnections is the lack of practical optoelectronic design that is compatible with the modern VLSI processing technology and low cost. Our research also focuses on the low-cost high-speed design of Si/SiGe based photodetectors in the mainstream CMOS, and constructing passive photonic structures, including waveguides, couplers in practical systems for a useful optical interconnection scheme.

Monolithically Integrated SiGe HBT Photodetector and Optical Receiver {Anand Pappu, Tao Yin, Anthony Kopa, Paul Chen} [FINISHED]

Integration of photonics with CMOS electronics presents a major challenge to designers of micro-optoelectronic systems. A low-cost solution to this challenge has so far eluded researchers from academia and industry alike.

First, we designed a high performance SiGe photodetector based on HBT using IBM's SiGe BiCMOS technology. This phototransistor offers a high responsivity of 2.4A/W for 850nm due to the transistor’s intrinsic gain, a responsivity of 0.12A/W for 1060nm detection due to the Ge composition in the absorption layer. The -3dB bandwidth for a phototransistor with 6µm x 10µm aperture reaches 2.3GHz, and the speed scales with the parasitics; for a phototransistor with 2µm x 2µm aperture, the -3dB bandwidth is 7.7GHz.

To use the photodetector, we integrated it with a receiver circuit fully compatible with IBM's commercial BiCMOS6HP technology. With advantages including no post-processing, no wire-bonding to off-chip detector, and a low power supply of 2.5V, we offer significant cost advantages in optoelectronic receiver design.

We later designed another optical receiver in IBM BiCMOS7WL process with 0.18µm feature size. The optical receiver
operates with data rate up to 1 Gbps using the integrated SiGe HBT photodetector developed earlier. The receiver uses a single power supply of 1.8V, eliminating the need for a separate high supply voltage usually required by photodiodes. This optical receiver provides another step to enable high speed optical communication in commercial silicon technologies.

Integrated Polymer Waveguide with SiGe Phototransistors and SiGe MOW {Tao Yin, Anthony Kopa} [FINISHED]

The SiGe base layer forms an internal waveguide with the cladding Silicon emitter and collector layers in the phototransistor structure. This waveguide effectively ensures the base absorption for lateral detection, as well as coupling to the base layer from a surface waveguide. As is known, the lateral detection is desirable to achieve high responsivity by utilizing the device length for absorption laterally while maintaining the high speed carrier transportation vertically. The picture below showed an integrated phototransistor with polymer waveguide, and the testing result shows an improvement in the 1310nm detection in this lateral detector comparing to the vertical illumination on similar devices. In addition, a SiGe MQW phototransistor integrating with the polymer waveguide is currently pursued to increase the long wavelength responsivity and enhance the waveguiding and coupling effect.

Electronic-Photonic Integrated Circuits (EPIC) {Anthony Kopa} [FINISHED]

The OEVLSI lab is a member of an interdisciplinary team working to develop an EPIC or Electronic-Photonic Integrated Circuit. The group includes academic, industrial, and defense partners. The goal is similar to the electronic idea of SoC - System on a Chip - but including active and passive photonic elements. Our goal is to combine all the elements necessary for optical signal processing - optical filters, waveguides, modulators, photodetectors, and CMOS electronics - into a fully functioning system all on a single silicon chip. We are working closely with our partners to develop the circuitry for very high speed (>10GHz), fully analog optical modulation and detection.

High Precision Frequency Control {Zhongtao Fu, John Lee, Woradorn Wattanapanitch, Eugene Minh} [FINISHED]

Chip scale high precision clocks have potential to improve the mobility of any systems and platforms with sophisticated RF communication or navigation requirements. The development of chip-scale atomic clocks requires high precision frequency locking circuits that are capable of low power operation. We are working on the control circuitry for a Chip Scale Atomic Clock project based upon a micro-cavity filled with Rubidium. A 6.8GHz Low power low phase noise PLL has been designed in Silicon on Sapphire 0.25µm technology.

Silicon on Sapphire Receiver Array {Zhongtao Fu} [FINISHED]

The differential optical receiver shown is based upon a novel cross-coupled architecture with controlled positive feedback and consumes 2.5 mW when operated at near gigabit rates, with bit error rates of better than 10-12. The transparency of the sapphire substrate facilitates system integration and packaging.

The 0.25 µm SOS CMOS 10 Gbps Receiver Project {Paul Chen, Anand Pappu, Woradorn Wattanapanitch} [FINISHED]

Bulk-less Silicon-on-Sapphire (SOS) provides reduced parasitic capacitances, and improved device isolation, enabling the design of low power, high-speed CMOS circuits. In this project, we explore the potential of designing 10Gbps optical receivers in a 0.25µm SOS process. This would be the first 0.25µm 10Gbps CMOS receiver, indicating a path to a lower cost transceiver for optical communication in this technology. We use various techniques to improve the gain-bandwidth-product (GBP) of the front-end and the limiting amplifier. The chip is fabricated by Peregrine Semiconductor and preliminary testing has shown the chip working at high data rates. The transparent sapphire substrate allows the photodetector to be flip-chip bonded on top of this chip and input light signal is being directed at the chip from behind.