Research

Introduction

Optics is used extensively in telecommunication for high speed and high broadband , and is playing an increasing role in short distance communication at backplane, rack and board level. The optical interconnection can potentially solve the problems of latency, wave reflection, cross-talk and impedance matching etc. that are limiting electrical interconnections based on its physical advantages of high carrier frequency and short wavelength. However, optics replace metal wires and be used in the territory of integrated circuits (IC)

Table of Contents

1. Ultra Low Power Impulse Radio Based Transceiver for Sensor Networks
2. Performance Evaluation with On-chip Optics for Future Bus Based CMPs
3. Short Link Optical Interconnects for Multi-core Processor Design
4. Circuits Design with Reduced Process Variation
5. Low Power Receiver for Wireless Sensor Networks
6. Electrical Isolation and On-Chip Interconnects
7. Monolithically Integrated SiGe HBT Photodetector and Optical Receiver
8. Integrated Polymer Waveguide with SiGe Phototransistors and SiGe MOW
9. Electronic-Photonic Integrated Circuits (EPIC)
10. High Precision Frequency Control
11. Silicon on Sapphire Receiver Array
12. The 0.25 µm SOS CMOS 10 Gbps Receiver Project

Ultra Low Power Impulse Radio Based Transceiver for Sensor Networks {Xiao Wang and Rajeev Dokania}

Ultra-wideband (UWB) radio has been proposed as a method for short range wireless communications. The low duty cycle nature of UWB can in principle, lead to large power savings by allowing power hungry RF subsystems to remain inactive for long periods of the transmission. To date, this power savings potential has not been realizable because the nature of UWB communications necessitates time synchronization between transmitter and receiver. To achieve this time synchronization, proposed UWB architectures have invariably used fast ADCs, high performance PLLs, and DSP back-ends. These components increase the overall power requirement. Achieving synchronization without the use of these components would tremendously lower the power requirement of any wireless transceiver. We propose using the pulse coupled oscillator (PCO) phenomenon as such an alternative synchronization scheme. Sensor network nodes implementing the PCO state function are guaranteed to converge towards phase lock, with no need for a PLL or any high speed components. So far we have demonstrated synchronization both on breadboard and in simulation in the IBMCMOS7RF process. The next step is to use this synchronization to demonstrate low power active communications in the 10-20 µW range.

Performance Evaluation with On-chip Optics for Future Bus Based CMPs {N. Kirman, M. Kirman, Rajeev Dokania, Matthew A. Watkins}

Technology scaling will soon allow tens or even hundreds of cores on a die. With so much of computation power on a single die comes the requirement for being able to feed them with data adequately. This poses problems for both off-chip and on-chip bandwidths. For the off-chip bandwidth, which is severely constrained by off-chip electrical data speed and pin-bandwidth, researchers are already looking at optics. In this collaborative project we go one step further and make a case for on-chip optical interconnect for future CMPs to move the data around different caches in a coherent manner. Within reasonable area and power constraints we conceptualize a hybrid electro-optical bus for on-chip communication. We then assess performance of the proposed architecture against the baseline electrical interconnects for future generation of technology.

Short Link Optical Interconnects for Multi-core Processor Design {Mustansir Mukadam}

The increasing need for high speed communication among cores in a multiprocessor system and the limitations of supporting such data rates with a purely electrical medium, has seen the shift to an opto-electronic communication backplane. The aim is to integrate all elements necessary for this form of communication - modulators, waveguides, photo detectors, receivers - for a low power (1fJ/bit), high speed ( > 10Gbps) application. The OEVLSI lab is part of an interdisciplinary team working on developing a multi-core processor with on-chip optical interconnects to support such design goals.

Circuits Design with Reduced Process Variation {Anand Pappu, Xuan Zhang}

With technology scaling, circuit engineers face tremendous challenges in designing robust circuits. Among all the circuit-design challenges posed by deep sub-micron technologies (tolerating process variations, managing power budgets, meeting performance goals and overcoming short-channel effects), tolerance to process variations is emerging as the most important one. This is especially true for analog circuits; on-die and wafer-scale variations in transistors can result in a number of problems including unpredictable bias conditions, band width, skew, VCO frequency and tuning range. These challenges are complex and necessitate design-stage statistical analysis to determine

Figure 2. Top histograms show the spread of transistor current in two wafer runs. Bottom histograms show the output current of our addition-based circuit. We see improvement of around 20% in each wafer run and 2x improvement across wafers, proving the operation of our circuit

conditions for maximum yield.

We start from building a current source with reduced variation. The histogram showed in Figure 1 illustrates how transistor output current may vary across multiple wafer runs, which is a vivid example of process variation.

Keeping the process mismatch and variation in mind, we introduced a methodology for circuit design and also came up with an addition based current source design that could alleviate the variation problem. The experiment result of our circuit is shown in Figure 2.

Our next step is to come up with more building blocks with low variation, and hopefully to set up a whole tool kit for analog circuit design.

Figure 1. Transistor output current across multiple wafer runs and for three specific runs.

Low Power Receiver for Wireless Sensor Networks {Zhongtao Fu}

Wireless sensor networks are networks composed with micro-sensors and wireless communication transceivers. These small devices are extremely low power and cheap with the potential to be disseminated in large quantities. Inspired engineers can easily find applications of data gathering for the medical health care, traffic control and environmental monitoring. These nodes, powered by environment scavenged energy or battery, require power consumption to be around 100µW or less. Since the Phase Locked Loop (PLL) is an essential building block of these transceivers, the low power VCO and PLL designs have drawn the most attention for this application. New methodologies, matrix and circuits are under investigation for this goal.

Electrical Isolation and On-Chip Interconnects {Anand Pappu}

At distances much shorter than one meter, delay and power consumption inherent to the electrical-to-optical and optical-to-electrical conversion circuitry degrade the performance of optical point-to-point signaling. However, by utilizing other advantages of optical signaling such as electrical isolation, we show in theory that even links shorter than 1 cm can demonstrate a clear advantage over electrical links [1,2]. In addition, we designed and fabricated proof-of-concept circuits to validate our theory and demonstrate the advantages of electrical isolation [3].

• [1] Anand Pappu and Alyssa Apsel, “Electrical Isolation and Fan-out in Intra-chip Optical Interconnects”, Proceedings of the International Conference on Circuits and Systems 2004
• [2] Anand Pappu and Alyssa Apsel, “Analysis of Intra-Chip Electrical and Optical Fanout”, Submitted to Applied Optics, December 2004
• [3] Anand Pappu and Alyssa Apsel, “A Low-Power, Low-Delay TIA for On-Chip Applications”, Conference on Lasers and Electro-Optics, May 2005

However what is stopping the development of optical interconnections is the lack of practical optoelectronic design that is compatible with the modern VLSI processing technology and low cost. Our research also focuses on the low-cost high-speed design of Si/SiGe based photodetectors in the mainstream CMOS, and constructing passive photonic structures, including waveguides, couplers in practical systems for a useful optical interconnection scheme.

Monolithically Integrated SiGe HBT Photodetector and Optical Receiver {Anand Pappu, Tao Yin, Anthony Kopa, Paul Chen}

Integration of photonics with CMOS electronics presents a major challenge to designers of micro-optoelectronic systems. A low-cost solution to this challenge has so far eluded researchers from academia and industry alike.

First, we designed a high performance SiGe photodetector based on HBT using IBM's SiGe BiCMOS technology. This phototransistor offers a high responsivity of 2.4A/W for 850nm due to the transistor’s intrinsic gain, a responsivity of 0.12A/W for 1060nm detection due to the Ge composition in the absorption layer. The -3dB bandwidth for a phototransistor with 6µm x 10µm aperture reaches 2.3GHz, and the speed scales with the parasitics; for a phototransistor with 2µm x 2µm aperture, the -3dB bandwidth is 7.7GHz.

To use the photodetector, we integrated it with a receiver circuit fully compatible with IBM's commercial BiCMOS6HP technology. With advantages including no post-processing, no wire-bonding to off-chip detector, and a low power supply of 2.5V, we offer significant cost advantages in optoelectronic receiver design.

We later designed another optical receiver in IBM BiCMOS7WL process with 0.18µm feature size. The optical receiver

operates with data rate up to 1 Gbps using the integrated SiGe HBT photodetector developed earlier. The receiver uses a single power supply of 1.8V, eliminating the need for a separate high supply voltage usually required by photodiodes. This optical receiver provides another step to enable high speed optical communication in commercial silicon technologies.

Integrated Polymer Waveguide with SiGe Phototransistors and SiGe MOW {Tao Yin, Anthony Kopa}

The SiGe base layer forms an internal waveguide with the cladding Silicon emitter and collector layers in the phototransistor structure. This waveguide effectively ensures the base absorption for lateral detection, as well as coupling to the base layer from a surface waveguide. As is known, the lateral detection is desirable to achieve high responsivity by utilizing the device length for absorption laterally while maintaining the high speed carrier transportation vertically. The picture below showed an integrated phototransistor with polymer waveguide, and the testing result shows an improvement in the 1310nm detection in this lateral detector comparing to the vertical illumination on similar devices. In addition, a SiGe MQW phototransistor integrating with the polymer waveguide is currently pursued to increase the long wavelength responsivity and enhance the waveguiding and coupling effect.

Electronic-Photonic Integrated Circuits (EPIC) {Anthony Kopa}

The OEVLSI lab is a member of an interdisciplinary team working to develop an EPIC or Electronic-Photonic Integrated Circuit. The group includes academic, industrial, and defense partners. The goal is similar to the electronic idea of SoC - System on a Chip - but including active and passive photonic elements. Our goal is to combine all the elements necessary for optical signal processing - optical filters, waveguides, modulators, photodetectors, and CMOS electronics - into a fully functioning system all on a single silicon chip. We are working closely with our partners to develop the circuitry for very high speed (>10GHz), fully analog optical modulation and detection.

High Precision Frequency Control {Zhongtao Fu, John Lee, Woradorn Wattanapanitch, Eugene Minh}

Chip scale high precision clocks have potential to improve the mobility of any systems and platforms with sophisticated RF communication or navigation requirements. The development of chip-scale atomic clocks requires high precision frequency locking circuits that are capable of low power operation. We are working on the control circuitry for a Chip Scale Atomic Clock project based upon a micro-cavity filled with Rubidium. A 6.8GHz Low power low phase noise PLL has been designed in Silicon on Sapphire 0.25µm technology.

Silicon on Sapphire Receiver Array {Zhongtao Fu}

The differential optical receiver shown is based upon a novel cross-coupled architecture with controlled positive feedback and consumes 2.5 mW when operated at near gigabit rates, with bit error rates of better than 10-12. The transparency of the sapphire substrate facilitates system integration and packaging.

The 0.25 µm SOS CMOS 10 Gbps Receiver Project {Paul Chen, Anand Pappu, Woradorn Wattanapanitch}

Bulk-less Silicon-on-Sapphire (SOS) provides reduced parasitic capacitances, and improved device isolation, enabling the design of low power, high-speed CMOS circuits. In this project, we explore the potential of designing 10Gbps optical receivers in a 0.25µm SOS process. This would be the first 0.25µm 10Gbps CMOS receiver, indicating a path to a lower cost transceiver for optical communication in this technology. We use various techniques to improve the gain-bandwidth-product (GBP) of the front-end and the limiting amplifier. The chip is fabricated by Peregrine Semiconductor and preliminary testing has shown the chip working at high data rates. The transparent sapphire substrate allows the photodetector to be flip-chip bonded on top of this chip and input light signal is being directed at the chip from behind.