As IC applications have multiplied over the past decade, pushing CMOS electronics beyond the PC and into everything from greeting cards to the human body, so have problems associated with nano-scale high performance CMOS. The quest for improved performance, previously masked by the progression of Moore’s law, now calls for renewed creativity and the development of fundamentally new approaches to circuit and architecture design. In our group, we consider how the progression of CMOS digital electronics and devices optimized for digital performance has affected mixed signal circuit design. We conduct research investigating new approaches to cost effective design that leverage today’s technology but achieve improved performance per unit power. We look at how problems resulting from device scaling such as process variation, noise, and reduced analog performance can be addressed with skillful analog and mixed signal design.

Active Research Projects:

Completed Research Projects:

  • Performance Evaluation with On-chip Optics for Future Bus Based CMPs
  • Short Link Optical Interconnects for Multi-core Processor Design
  • Low Power Receiver for Wireless Sensor Networks
  • Electrical Isolation and On-Chip Interconnects
  • Monolithically Integrated SiGe HBT Photodetector and Optical Receiver
  • Integrated Polymer Waveguide with SiGe Phototransistors and SiGe MOW
  • Electronic-Photonic Integrated Circuits (EPIC)
  • High Precision Frequency Control
  • Silicon on Sapphire Receiver Array
  • The 0.25 µm SOS CMOS 10 Gbps Receiver Project